Brief Description of the Prior Art
Current mode logic (CML) or emitter coupled logic (ECL) circuits are commonly used in high speed applications operating in the GHz frequency range. In these circuits, to reduce the storage time, caused by the presence of minority carriers, the transistors are usually not allowed to operate in hard saturation. Storage time, which is the time before an on transistor starts to turn off, tends to decrease the speed of the circuit. In CML circuits a constant current is maintained in the emitter legs of the transistors with current switching from one transistor leg to another depending on the states of the input signals.
FIG. 1 (prior art) shows one version of a conventional OR/NOR gate implemented in MOS CML. The circuit is made up of stacked transistors pairs 3-4 and 5-6 which allows for differential inputs A/A and B/B to be applied, respectively. Current source 7 maintains a constant current I through the legs of the circuit at all times. There are three paths, one of which will always be enabled, for current to flow through the circuit, as follows: a) through resistor 1 and transistors 3 and 5, b) through resistor 1 and transistor 6, and c) through resistor 2 and transistors 4 and 5. In the circuit, the signals at A/A have to operate with a DC voltage shift relative to the signals at B/B. For very low V.sub.DD voltages there is limited headroom available for this voltage shift in order to maintain proper drain-to-source voltage, V.sub.ds, across the transistors and this usually limits the number of complementary inputs to two. One way to accomplish this voltage shift is with the use of source followers but these add complexity and tend to slow down the circuit. This circuit provides both OR (A+B) and it's complementary NOR (A+B) outputs. A truth table for the circuit is included below.
OR NOR A B A + B A + B 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 0
Here the difference between a logic 0 and logic 1 is small, on the order of 400 to 800 mVolts. Some drawbacks of the circuit include:
1. Not suitable for ultra-low voltage operation of &lt;1.2 volts due to the circuit's limited headroom for V.sub.ds across the stacked transistors pairs.
2. Limited to two inputs, A/A and B/B.
3. Signals B and B have to be DC shifted compared to signals A and A.
Although this gate is inherently fast, the required level shifting circuitry, not shown, tends to slow the overall operation of the circuit.
FIG. 2 (prior art) shows another commonly used CML circuit which overcomes the problems of the circuit in FIG. 1, but as will be discussed, has its own set of problems. Singled-ended input signals A and B are inserted at the gates of transistors 10 and 11. Resistor 8 connects the drains of transistors 10 and 11 to V.sub.DD to provide a path for current to flow into current source 13 when either or both of these inputs are high (logic level 1). This circuit is not limited to two inputs, although only two are shown, and overcomes the DC level shifting problem of the previous circuit by operating all the transistors at the same voltage level. In addition, transistor 12 and resistor 9 are used to provide another path for current I to flow into current source 13 when both of the input transistors 10 and 11 are OFF. The V.sub.ref input is a DC level which biases transistor 12 at the mid-point of the A and B input signal's voltage swing. If both A and B inputs are low (logic level 0), all the current I will flow through V.sub.ref transistor 12. Then as inputs A and/or B turn on (logic level 1) current will switch and flow through transistors 10 and/or 11. As with the previous circuit, both OR (A+B ) and it's complementary NOR (A+B) outputs are generated. Although this circuit does overcome the problems of the previous circuit, it has its own drawbacks, as follows:
1. A reference voltage at mid-signal is required.
2. The circuit only allows single-ended inputs which usually implies larger input swings. This in turn can increase the voltage supply size and reduces the circuit speed. An alternative sometimes used is to keep the input swing constant and increase the size of the MOS transistors, but this also negatively impacts the circuit speed.
3. Less immunity to noise due to single-ended operation.
4. Circuit delay is more sensitive to the parasitic elements at node N1 since the node has more movement with V.sub.ref remaining constant while the inputs A and B move.